Job Description : Exp : 2 to 8 YearsLocation : BangaloreRole and Responsibilities :
Experience with at least one characterization tool (Silicon Smart / Liberate) for complete characterization of a library to generate the front end and back end views.
Understanding of CCS, ECSM liberty models, LVF, Verilog models, statistical characterization.
Understanding of characterization methodologies for combinational, sequential cells and timing, power, capacitance models.
Knowledge of cell characterization flows and methodologies, library verification and validation.
Familiarity with circuit simulators, liberty syntax, library compiler, design compiler.
Basic understanding of static timing analysis and synthesis.
Scripting skills with python,shell,tcl.Skill Requirements :
Characterization and generation of front end and back end views for standard cell libraries
Custom cell characterization setup and flows
Library verification and validation
Automation for the QA checks, for small tasks in setting up the flows for characterization and QA
Documentation of and recording the issues, debugs, solutions and new / enhanced work flows
Mentor and enhance the skill set of junior team membersGood to have : Automation skills like python modules. APL, CCSP. PGV generation flow knowledgeQualifications : B. Tech / B. E / M. Tech / M. E
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Standard Cell Characterization • Bengaluru, Karnataka, India
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