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Senior Chip Lead ( Senior Director level)

Senior Chip Lead ( Senior Director level)

Mulya TechnologiesGreater Hyderabad Area, India
27 days ago
Job description

Senior Chip Lead / Chip Lead (Sr Director / Director)

Hyderabad

A Hyderabad based SoC Turnkey design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices.

Job Description :

We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM.

Job responsibilities include :

  • Driving the specification of the chip with architect and design leads – eventually cascading into block specifications.
  • Make PPA decisions for the chip.
  • Defining multiple development checkpoints – for IP / SoC Design / DV / PD
  • Come up with overall project plan and cascaded schedule details for other teams
  • Work with Analog / Digital IP teams to laydown integration details for the IPs.
  • Drive the full chip floorplan / bump maps and provide area / floorplan targets to IP teams.
  • Define the sign-off criteria for the device.
  • Define the SoC verification plan items / scenarios to be covered.
  • Assist / Review the micro architecture definition for digital blocks
  • Define RTL Quality gate criteria for integration – Lint / CDC /
  • Drive the timing constraints / timing analysis / closure activities.
  • Define the DFT targets for the chip and cascade that into activities needed on the DFT front.
  • Work with PD enginers to get the physical design closure.
  • Handle tapeout formalities

Qualifications :

  • Close to 15 years of solid experience in SoC design.
  • A self starter. Candidate ready to define things where none exist.
  • Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort.
  • Proven ability to develop architecture and micro-architecture from specifications.
  • Understanding of chip I / O design and packaging is advantageous.
  • Experience in reviewing top-level test plans.
  • Expertise in Synopsys Design Compiler for synthesis and formal verification.
  • Strong working knowledge of timing closure processes.
  • Experience with post-silicon bring-up and debugging.
  • Familiarity with SoC integration challenges.
  • Knowledge of design verification aspects is essential.
  • Experience from SoC specification to GDS and commercialization is highly desired.
  • Ability to make timely and effective decisions, even with incomplete information.
  • Demonstrated expertise in specific technical areas, with significant experience in related fields.
  • Provide direction, mentoring, and leadership to small to medium-sized teams.
  • Strong communication and leadership skills are necessary for effective collaboration with program stakeholders.

    • Contact : Uday Bhaskar

    Mulya Technologies

    "Mining the Knowledge Community"

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    Senior Director • Greater Hyderabad Area, India