ASIC Engineering Director

Hiring : ASIC Engineering Director :

Job Location : Hyderabad

Experience : 20+Years

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it.

KEY EXPERTISE :

• Seasoned ASIC Front End leader with 20 years of cross domain experience ranging from architecture, uArch, IP / Sub- systems / SOC / chiplets design / integration, RTL coding, Synthesis, CDC, timing, power analysis, system / IP verification, Silicon Bring up.
• Proven track record of leading the design and development of complex IPs, sub-systems, chiplets for SOCs in the multiple domains like PCIE, USB, UCIE, ARM / x86 CPUs, RISC-V, VPU / NPU, GPU, LSIO, NOC, Fabrics, AMBA buses, DRAM, SD / SDIO / eMMC etc. Responsible for defining the technical direction of ASIC designs and collaborating with cross- functional teams to ensure successful ASIC implementation.
• Demonstrated strong leadership, project timelines & resources management and team management skills, and the ability to influence the technical strategy of the organization.
• Familiar with ASIC verification methodologies, DFT, Physical design and board design which help in influencing cross functional teams in getting desired results.
• Excellent execution capabilities to handle multiple domains in multiple projects simultaneously.
• Delivered superior results through team collaboration and diversity of thought. Always open to learn new technologies to grow in technical breadth and depth.
• Managed development of multiple sub-systems and IPs designed from scratch for Intel IOT (Elkhart Lake), Edge (Reefbay), dVPU / NPU (Arrow LakeR), GPU (DMR-D), Media (MTL-D), Smart NIC (Altera NIC), Palm Ridge, Mount Morgan IPU SoCs which are executed in advanced technology nodes of both Intel (18A, 3nm, 5nm) and TSMC (N3e, N5, N6).
• Have hands on experience in chiplets, Sub-systems and IP development (micro-architecture development, 3rd party IP integration (Synopsys, Verisilicon. SiFive RISCV, ARM cores etc.,), RTL implementation, synthesis, static timing analysis, Power analysis, system / IP level verification, FPGA emulation, Si bring-up) and SoC integration flows and methodologies.
• Led 30+ engineer design team and have good experience in working with cross-functional teams and cross BU teams across multiple geos, resulting in good collaboration and accelerated time to market.
• Led IP development (RTL design, Lint, CDC, Synthesis, timing, unit level and system level verification) of various IPs in Nvdia Tegra SoC processors (from first generation [APX] to ninth generation [Xavier]) and Cisco NIC chips.
• Have good working experience on low power design methodologies (clock gating, power gating, multi-vt and DVFS) used in mobile SoCs.
• Designed couple of modules in Tegra SoC like DMA engine, SD / SDIO / eMMC5.2 host controller and bus-bridges for Nvidia proprietary buses. Worked on architecture, micro architecture, RTL design and timing analysis. Familiar with automotive electronics ISO26262 safety requirements.
• Was Executive member from Nvidia in SD card org and JEDEC (eMMC) forum. Participated in SD / SDIO4.x, SD host4.x and eMMC5.x specification development.
• Working experience with cross functional teams like back end, analog I / O pad and SW teams to ensure IP requirements are met at each stage. Have working experience in developing tree build and regression infrastructure.
• Have hands on experience in ASIC verification also - Test Planning, Develop Directed, Random and System-level (soc level) Test Cases; Design Test Bench using System Verilog; Develop Random Test environment; Execute Code Coverage & Analyse Reports, Execute Gate-level Simulations; Execute Functional & Regression Tests.
• Good Team Player : Participated and lead the effort of SD4.x / eMMC5.x host controller design and verification. Detail oriented go- getter with Fast Learning Curve and strong analytical, decision making, problem solving, visualizing, negotiating, communication & interpersonal skills.
• Mentored engineers, designed IP / SS schedules with proper staging plan with cross team dependencies, identified and solved technical issues, and ensured development of high-quality products.

(ref : hirist.tech)