Senior Design Verification Engineer

JD Design Verification

• Understanding the business requirements and functional specifications of the IPs, subsystems and SOC
• Creating Verification Environment Architecture document
• Reviewing and Revising : working towards meeting agreed upon acceptance criteria
• Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification
• Performing RTL simulations using Synopsys and Cadence simulators
• Debugging and resolving problems found by simulations .Performance test plan development and maintenance
• Development of transactors, monitors and models for performance verification.
• Implement performance verification flow including monitoring, synchronization, reporting and self-checking mechanisms
• Provide full report of performance metrics and bottlenecks
• Tracking tickets and code releases using Bug Tracking tool and GIT
• Performing UPF (Unified Power Format) based Power Aware simulations
• Coding of Assertion and Functional Coverage bins in SVA (System Verilog Assertions)
• Code & Functional Coverage Closure

Performing Gate Level simulations .Preparing and conducting reviews of Verification Sign-off documents to ensure SOC tape-out quality