SOC Engineering, Staff Engineer

Job Description and Requirements

The role is for RTL Design and Signoff of IP / Subsystem / SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies.

As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint / CDC / RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality, and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors.

Responsibilities

• Perform RTL Quality Signoff Checks such as LINT, CDC, RDC.
• Understand the design / architecture and develop timing constraints for synthesis and timing.
• Run preliminary synthesis to ensure that the design can be synthesized as intended.
• Run formality to ensure equivalence of RTL and gates.
• Integrate IPs in SoCs / Subsystems and create RTL design as per need of the customer.

Skills Required

Semiconductor, Chip Design, Soc, Circuit Designing, silicon, Embedded Circuits