(15h Left) Analog / Mixed-Signal Functional Verification

Job Function

Work on Analog / Mixed-Signal Functional Verification for Analog / Mixed-Signal IPs, such as SERDES, Sensors and beyond. The candidate will work with digital design, analog design, analog behavioral modeling and other design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to the entire life cycle of AMS Functional Verification process, from understanding specification, test planning to coverage closure and post silicon debugging support, to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.

Skills / Experience

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, digital design, and UVM-based design verification methodologies.
• Proficient on using design and verification languages : UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals,
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc.
• Power-aware simulations and gate level simulations is a plus
• Scripting and automation skills : Unix / Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Familiar with programming languages : C, C++, and / or SystemC is a plus.

Responsibilities

Education Requirements