IC Design Engineer

Responsibilities

• Understanding of SoC for top-down / bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed / adapt to existing flows for re-use
• Must be proficient in any of the Cadence / Synospys / Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his / her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications :

Skills Required

Eda, Analytical Skills, TAT, Soc