STA - Synthesis Design Engineer 2
ConfidentialHyderabad / Secunderabad, Telangana30+ days ago
Job descriptionExperienced in synthesis and timing closure Good to have experience in LEC, CLP Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. scripting and automation Bachelors with 2 years of experience or Masters degree with 1 years of experience in Electrical Engineering
THE ROLE :
The focus of this role is to execute the front end implementation of sub-blocks or IP. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA / Timing closure. Co-ordinate with design team and PNR teams.
KEY RESPONSIBILITIES :
- Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA / Timing closure
- Collaborate with designer and PNR teams to achieve closure.
- Execute as per schedule.
- Complete quality delivery for synthesis and timing closure.
- Debug and resolve technical issues
PREFERRED EXPERIENCE :
ACADEMIC CREDENTIALS :
Skills Required
lec, Clp
Create a job alert for this search
Design Engineer • Hyderabad / Secunderabad, Telangana