SMTS Silicon Design Engineer

Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities.

KEY RESPONSIBILITIES :

• Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff
• Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure.
• Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA.
• Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM / IR and signoff.
• Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk

PREFERRED EXPERIENCE :

ACADEMIC CREDENTIALS :

Skills Required

Python Scripting, Physical Design, Timing Closure, floorplanning, synopsys tools