Lead Engineer (3 Days Left)

ob Title : Physical Design Lead

Location : [Insert Location]

Department : Engineering / ASIC Design

Experience : 5+ years in physical design

Key Responsibilities :

Required Qualifications & Skills

• Bachelor’s or Master’s degree in ECE / Electronics / EEE or related field.
• 3 + years of physical design / back-end implementation experience (block-level or SoC) in VLSI.
• Proven experience in floor-planning, placement, CTS, routing, timing closure, sign-off physical verification (DRC / LVS / antenna).
• Hands-on with EDA tools : Synopsys, Cadence, Mentor (specifically tools like ICC2, Fusion Compiler, Innovus, PrimeTime, Tempus).
• Strong understanding of timing closure concepts : setup / hold violations, timing paths, PVT corners, multi-mode multi-corner.
• Good knowledge of power, area, performance trade-offs; power-optimization techniques.
• Good scripting knowledge (Tcl, Perl, Python) for automation of PD flows.
• Ability to analyze and debug physical design issues such as congestion, IR-drop, EM, signal integrity, crosstalk.
• Excellent communication skills and ability to work in cross-functional teams.

Key Responsibilities