Verification Manager
Bengaluru / Hyderabad
About Omni Design Technologies
Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT).
Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts.
Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers.
Verification Manager
Hyderabad / Bangalore
SOC Development – Engineering /
Full-time /
Hybrid
The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality for mixed signal SOC. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM / RISC-V processor technology and AMBA AHB / AXI / APB along with high-speed interfaces like PCIe, MIPI, USB, Ethernet, Mobile DDR and Quad / Octa-SPI and peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN, Ethernet, PCIe, UCIe as well as Mixed Signal AMS simulation environment.
Role and Responsibilities
Qualifications and Skills
Expectations
Develop the Test benchses for AMS and FC simulations
Be UPF Aware.
Develop the tests to get 95+% coverage for the simulations
Work with Design team to debug any failures
Integrate and run the BIST and DFT gate level sims.
Do code, line and toggle coverage and other metrics.
Run daily and weekly regressions and publish results
Responsible for FC RTL, Gate level simulations
Be a mentor and lead a team of Verification engineers
Work with Systems and Test engineering team to help validate the parts and release them to production
Contact : Uday
Mulya Technologies
"Mining The Knowledge Community"
Manager Verification • Hyderabad, India