Silicon Validation Engineer

Job Description :

• Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality.
• Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or C++ verification environments. Construct SystemVerilog and / or C / C++ models and test sequence libraries for simulation.
• Build test bench components including agents, monitors, scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness.
• Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
• Develop high coverage and cost effective test patterns, and take part in ATE bring-up.
• Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs.

Preferred Experience :

Additional skills :

Educational background :