Senior Design Verification Lead (PCIE)

Eximietas Hiring Senior Design Verification Engineers / Leads (PCIE)

Experience : 8+ Years.

Location : Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.

Anyone with a Valid H1B or Already in US.

Job Description :

• Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans.
• Develop and implement comprehensive verification strategies , including test plans, testbenches, and coverage analysis, for both high-speed and low-speed peripherals (e.g., I2C, SPI, UART, GPIO, QSPI) as well as high-speed protocols (e.g., PCIe, Ethernet, CXL, MIPI, DDR, HBM ).
• Conduct Gate-level simulations and power-aware verification using tools like Xprop and UPF .
• Collaborate closely with cross-functional teams, including architects, designers , and pre / post-silicon verification teams , to ensure alignment and seamless integration of verification efforts.
• Analyze and implement System Verilog assertions and functional coverage (code, toggle, functional) to ensure thorough verification of design functionality.
• Provide mentorship and technical guidance to junior verification engineers, helping to elevate team performance.
• Lead and manage a dynamic team of verification engineers, fostering a collaborative and innovative work environment .
• Ensure that all verification signoff criteria are met, with clear and comprehensive documentation.
• Demonstrate strong dedication, work ethic, and commitment to meeting project goals and deadlines .
• Uphold quality standards and implement best test practices , contributing to continuous improvements in verification methodologies.
• Work with verification tools from Synopsys and Cadence , including VCS and Xsim .
• Integrate third-party VIPs (Verification IP) from Synopsys and Cadence to enhance verification coverage.

Qualifications :