Physical Design Engineer

Experience

• 3-6 years

Role and responsibility :

technologies (28nm,16nm,14nm & below ).

including Synthesis, Floor Planning, Power Plan, Integrated Package and

Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis,

complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR

Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC,

ERC, LVS), DFM and DFY and Tapeout.

electrical rules in deepsub micron processes required. Understanding of process

variation effects, and experience in variations analysis / modeling techniques and

convergence mechanism would be a plus.

Qualification :