Strong background of ASIC Physical Design : Floor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.Hands-on experience on technology nodes like 7nm, 14nm, 10nm.Good knowledge of EDA tools from Synopsys , Cadence and MentorHands-on experience in floor planning, placement optimizations, CTS and routing.Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT / PTSI, TEMPUS, DC, RC, VOLTAS) Skills : - Responsive Design, Project coordination, Extraction, Competitor Analysis, EDA, floorplanning, 7nm, 14nm and 10nmSkills Required
Dc, Pt, Routing, Asic Physical Design, Cadence, Mentor, Signal Integrity, Rc, Static Timing, EDA Tools, Floor Planning, Synopsys, PTSI