Layout / Mask Designer 3_INR

Job Summary (List Format) :

1. Work with advanced process nodes (TSMC 16 / 12nm, 7nm, 5nm, 3nm and below; also Intel, Samsung, GF), with preference for TSMC 5nm / 3nm experience.

2. Design and develop critical analog, mixed-signal, custom digital blocks and provide full chip-level integration support.

3. Perform and manage verification flows including LVS, DRC, DFM, Antenna check, and EMIR.

4. Ensure on-time delivery and quality of block-level layouts.

5. Utilize Cadence VLE / VXL and Mentor Graphics Calibre DRC / LVS tools.

6. Hold a BE or MTech in Electronics / VLSI Engineering.

7. Communicate effectively and collaborate with cross-functional teams.

8. Require recent hands-on experience with lower technology nodes.

9. Work independently and take ownership of assigned tasks.

10. Have 4 to 8 years of relevant experience (flexible).

11. HBM (High Bandwidth Memory) and experience with analog blocks (regulators, charge pumps, power management) is a plus.

12. Face-to-face interviews in Hyderabad are highly recommended.