Senior Engineer - PD

Job Requirements

Job Title : Senior Engineer - Physical Design (PD)

Job Type : Full-Time

We are seeking a highly skilled and experienced Physical Design Lead in VLSI with a minimum of 3-7 years of experience to join our team. As the Lead Engineer in Physical Design, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex VLSI designs.

Esponsibilities

Lead the physical design (PD) team through complete ASIC / SoC implementation flow.

Handle floorplanning, partitioning, placement, CTS (Clock Tree Synthesis), routing, and sign-off activities.Drive timing closure, power optimization, area optimization, and DRC / LVS clean designs.Collaborate with RTL, DFT, verification, and package teams to achieve project goals.

Manage block-level and chip-level physical design, including hierarchical and flat methodologies.

Perform static timing analysis (STA), power analysis, and signal integrity checks.Ensure physical verification, IR drop, and EM analysis closure.

Guide junior engineers, review their work, and provide technical mentorship.Drive tool flow automation and efficiency improvements in PD.

Interface with customers / stakeholders for updates, reviews, and sign-off.

Required Skills

Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor).

Solid understanding of ASIC design flow and foundry process nodes (7nm / 5nm / 14nm or relevant).

Deep knowledge of STA, power analysis, IR / EM, and physical verification methodologies.Good experience in ECO (Engineering Change Order) flows.

Familiarity with scripting languages (TCL, Perl, Python) for automation.

Proven experience handling full chip / block-level PD independently.Strong problem-solving and debugging skills.

Good communication and leadership abilities to lead a PD team.

Education

B.E. / B.Tech or M.E. / M.Tech in Electronics, Electrical, or VLSI Design.

Work Experience

Required Skills :

Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor).

Solid understanding of ASIC design flow and foundry process nodes (7nm / 5nm / 14nm or relevant).

Deep knowledge of STA, power analysis, IR / EM, and physical verification methodologies.Good experience in ECO (Engineering Change Order) flows.

Familiarity with scripting languages (TCL, Perl, Python) for automation.

Proven experience handling full chip / block-level PD independently.Strong problem-solving and debugging skills.

Good communication and leadership abilities to lead a PD team.

Skills Required

Sta, power analysis, Mentor, Ir, Perl, Python, Tcl