Accelerated Design Verification

Reduced post-silicon bug escapes through early software-driven validation in emulationenvironments. (Accelerated Verification)

Cut SoC bring-up time by 50% by architecting a unified simulation-to-emulation testbenchwith reusable transactors.

Spearheaded the Accelerated verification plan for a next-gen ADAS SoC including usecaseslike Start Up, BOOTROM, Complex data path , Negative tests

Enabled 80% reuse of verification components across simulation, emulation, andprototype platforms through modular UVM design.

Successfully led a AV verification team of engineers across DV, emulationKey Skills

• Accelerated Verification :
• Synopsys ZeBu, Siemens Veloce
• Verification Methodologies :
• UVM, SystemVerilog, Acceleratable UVM, C based
• V&V Reuse & Bridging :
• Simulation-to-Emulation Flow, Coverage Continuity, TransactorDevelopment is desirable