(15h Left) Design Engineer

RTL coding, simulation / verification

Experience : 4+years

Location : Hyderabad

Required skill for the Job : Hands-on experience with AMD Xilinx development tools, Vivado and Vitis.

Preferred to have worked with AMD Xilinx evaluation boards before.

Experience in C bare-metal firmware development for IP testing and validation.

RTL coding, simulation / verification.

Knowledge of AMD SoC architectures : Versal ACAP, Zynq UltraScale+ MPSoCs

Hands-on experience on hardware platform bring-up and low-level debugging.

Familiar with using U-Boot, root file system, and device tree on AMD Xilinx hardware platforms.

Experience with version control systems, preferably Git.

Knowledge of Python, Bash, Perl scripting for testing and automation

Able to collaborate with cross functional teams.

Basic Job Deliverable : Develop Vivado and Vitis projects based on AMD Xilinx hardware platforms.

Perform hardware interfaces validation with compiled projects’ binaries.

Create documentation and debug / running scripts for repeatable validation flow.

Intersted,please drop your updated resume to janagaradha.n@acldigital.com