Layout / Mask Designer 2_INR

Job Summary (List Format) for the Provided Job Description :

• Develop and prepare standard cell (stdcells) layouts and detailed drawings of semiconductor devices from schematics and design geometry.
• Utilize CAD tools (primarily Cadence Virtuoso) for layout development and modifications.
• Check dimensions, write specifications, and verify completed drawings, artwork, or digitized plots.
• Perform physical verification activities, including DRC / LVS checks, for complex designs as per specifications.
• Develop and optimize standard cell layout libraries for advanced CMOS processes.
• Conduct layout area and routing optimization, considering design rules, yield, and reliability factors.
• Apply layout fundamentals such as electromigration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, and shielding.
• Interface and collaborate with circuit designers and CAD teams for schematic understanding and layout effects (speed, capacitance, power, area).
• Solve complex problems related to area, power, performance, and physical verification of custom layouts.
• Use verification tools, such as Mentor Caliber, for physical verification tasks.
• Demonstrate expertise in device matching, parasitic analysis, electron migration, and isolation techniques.
• Exhibit leadership qualities and ability to multitask as required.
• Work effectively in a team environment and provide technical guidance / support to team members.
• Self-motivated, hardworking, goal-oriented, with strong verbal and written communication skills.
• Knowledge of Skill coding and layout automation is a plus.

Mandatory Skillset :