Senior Physical Design Engineers – High-Speed Soc / Ip

Senior Physical Design Engineers – High-Speed SoC / IP (TSMC 5nm)

Remote (India) | Work Hours : USA / Canada Time Zone | Willing to Travel to the U.S. (US Visa beneficial)

Experience -8+ Years

We’re looking for Physical Design Engineers (8+ years) to join our high-speed SoC / IP development team in TSMC 5nm. The role involves full-chip floorplanning, placement, routing, and signoff for large-scale SoCs (~1 billion gates), ensuring timing, power, and area closure for high-speed IPs and SoCs.

The ideal candidate should have deep chip-level understanding, expertise in CTS, timing closure, DRC / LVS / ERC, and signal integrity, and be able to work independently as an individual contributor. Strong scripting skills (TCL, Python, Shell) are required to automate PD flows and handle large designs efficiently. You will collaborate closely with RTL, DV, and Analog teams to ensure seamless integration.

Skills Required :

• Hands-on experience with TSMC 5nm / advanced nodes and large-scale SoCs (~1B gates)
• Expertise in floorplanning, placement, routing, CTS, ECOs, STA, DRC / LVS / ERC
• Strong timing closure, power optimization, and signal integrity skills
• Strong scripting skills in TCL, Python, Shell to automate flows and handle large designs
• Tools : Synopsys IC Compiler II, Innovus, PrimeTime, Calibre
• Ability to work independently and coordinate with global cross-functional teams
• Flexible to work in USA / Canada time zones and travel to the U.S. if required