Senior Layout Design Engineer – SRAM Compiler

Position : Senior Layout Design Engineer – SRAM Compiler

Location : Bangalore

Experience : 7+ Years

Job Description :

• Strong hands-on experience in full-custom SRAM / memory layout, SRAM compiler blocks, bitcells, and periphery circuits.
• Expertise in physical verification (EM, IR, LVS, DRC), design-rule closure, debugging violations, and sign-off quality.
• Ability to work independently with circuit, architecture, and verification teams, ensuring layout quality and adherence to constraints.
• Proficiency with custom layout tools (Cadence Virtuoso), optimization flows, and handling complete end-to-end memory layout ownership.