Physical design engineer

Job Summary

We are seeking a highly experienced Senior Physical Design Engineer with a minimum of 10 years in the RTL to GDSII flow. This role requires hands-on expertise with Cadence Innovus , experience at N3 and below process nodes , and strong scripting and flow debugging skills.

Key Responsibilities

Lead physical design activities from RTL to GDSII, ensuring high-quality and timely project delivery

Execute floorplanning, placement, CTS, routing, and physical verification

Develop and maintain automation scripts to streamline physical design tasks

Collaborate with RTL, DFT, and verification teams to resolve design issues and achieve timing closure

Optimize for power, performance, and area (PPA) to meet design targets

Analyze timing, signal integrity, and power reports; implement necessary design changes

Mentor junior engineers and promote continuous learning and improvement

Stay current with physical design methodologies and integrate best practices

Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field

10+ years of experience in physical design with deep understanding of RTL to GDSII flow

Proven hands-on experience with Cadence Innovus

Demonstrated expertise in N3 and below technology nodes

Strong scripting skills in Tcl, Perl, or Python , with ability to debug and enhance design flows

Successful track record in timing closure, PPA optimization, and resolving complex design challenges

Solid grasp of digital design principles including clock distribution, signal integrity, and power analysis

Excellent problem-solving and communication skills

Preferred Skills

Knowledge of low-power design techniques

Familiarity with version control systems and collaborative development tools

Experience with physical verification tools such as Calibre or Mentor Graphic