Senior / Staff STA Engineer

Tenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. Engineers with a strong foundation in Static Timing Analysis (STA) and timing constraints . In this role, you’ll lead timing closure efforts across block and full-chip levels, working closely with physical design, RTL, and verification teams across multiple technology nodes, including 5nm and 3nm.

This role is onsite, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are :

• 5+ years of hands-on experience in STA for complex SoCs, spanning from block-level to full-chip analysis and closure.
• Proven expertise in developing and validating timing constraints (SDF / SDC) for various design modes and PVT corners.
• Comfortable using tools like PrimeTime, Tempus, or PTPX for timing signoff and power analysis.
• Strong scripting skills in Tcl, Perl, or Python to automate timing flows and custom reporting.
• Ability to collaborate across RTL, PD, DFT, and synthesis teams to debug and resolve timing issues efficiently.

What We Need :

What You Will Learn :