General Summary :
As a SoC Power & Architecture Engineer, you will collaborate with cross-functional teams to develop and optimize power architecture for mobile SoC ASICs. Your expertise will drive low-power design techniques and power management strategies that enhance chip efficiency and performance.
Skills and Experience :
- Required (4–12 years) :
- Low power intent concepts and languages (UPF or CPF)
- Power estimation and reduction tools (PowerArtist, PTPX, Calypto)
- Power dissipation and savings techniques, including dynamic clock and voltage scaling
- Power analysis (leakage and dynamic) and thermal impact evaluation
- Power software features for optimization
- Voltage regulators (Buck converters, Low Dropout regulators)
- ASIC power grids and PCB power distribution networks
- Preferred / Additional Skills :
- Mobile baseband application processor chipset and power grid knowledge
- UPF-based synthesis and implementation with Design Compiler
- Structural low power verification tools (CLP, MVRC)
- Excellent written and verbal communication skills
Responsibilities :
Define chip and macro-level power domainsConduct system-level power modeling and mixed-signal power analysisDesign power islands, power gating, and power isolation techniquesDevelop structural low-power design elements such as level shifters and isolation cell topologies with associated design rulesPerform architectural analysis and develop digital power optimization logic, circuits, and softwareCollaborate with Power Management IC developers for power grid planningCreate detailed architecture and implementation documentationEducation and Minimum Qualifications :
Required :Bachelor's degree in Computer Engineering, Electrical Engineering, or related field with 3+ years of hardware engineering experienceORMaster's degree with 2+ years of hardware engineering experienceORPhD with 1+ year of hardware engineering experiencePreferred :Master's degree in Computer Engineering or Electrical EngineeringSkills Required
power analysis, Synthesis, Estimation, Scaling, hardware engineering