Design Verification Engineer

We are seeking a proficient ASIC / SoC Verification Engineer with over 3 years of experience to oversee a team of 2–3 engineers. The perfect candidate should possess extensive practical knowledge in GLS (Gate-Level Simulation), adept at constructing test-benches from the ground up in System Verilog (SV) and UVM. They must excel in crafting verification plans and environments, leading debugging processes, providing mentorship to junior engineers, and exhibit top-notch communication skills along with effective cross-functional collaboration abilities. They must have test bench development experience with working on high speed protocols.