Job Details
Job Description :
Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Creates prototypes, simulates models, and specifies systems requirements. Prepares and designs logic diagrams and codes for implementing system design and test specifications. Delivers software models for device level bring up, including user visible functionality, timing, and power. Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Qualifications
Minimum Qualifications
Preferred Requirements
Job Type
Regular
Shift
Shift 1 (India)
Primary Location :
Bengaluru, Karnataka, India
Additional Locations :
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Skills Required
Synthesis, RTL Coding, Timing Closure, Digital Design
Design Engineer • Bengaluru / Bangalore, India