Senior Design Verification Engineer

Description :

Job Title : Senior Design Verification Engineer

Experience : 7- 10 years

Number of Positions : 3

Employment Type : Full-Time

About the Role :

We are seeking an experienced Senior Design Verification Engineer to join our dynamic semiconductor engineering team. The ideal candidate will have deep expertise in SoC and CPU verification, strong hands-on experience in SystemVerilog / UVM, and a solid understanding of computer architecture and cache-coherent systems. This is an individual contributor role requiring the ability to independently execute verification tasks while collaborating effectively within a cross-functional environment.

Key Responsibilities :

• Take ownership of assigned Design Verification (DV) tasks and deliver with minimal supervision.
• Collaborate with architects, logic designers, and other verification engineers to define and implement verification strategies.
• Develop comprehensive test plans, coverage plans, and checker plans to ensure first-pass silicon success.
• Build and maintain scalable testbenches using SystemVerilog and UVM methodologies.
• Develop test cases, functional coverage models, and SystemVerilog assertions (SVA).
• Perform debug and root-cause analysis of regression failures (Tests / Sequences, RTL, and C++ Models).
• Optimize regression performance by managing test / coverage grading, compute farm utilization, and disk efficiency.
• Drive code and functional coverage closure to meet verification quality targets.
• Support unit-level and subsystem-level verification and assist with integration-level debug.

Skills and Qualifications :

Domain Expertise :

Technical Skills :

Preferred Qualifications :

(ref : hirist.tech)