PMTS Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ PMTS SILICON DESIGN ENGINEER ABOUT THE DEPARTMENT Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for high performance, adaptive compute products for data center, embedded, gaming and PC markets. It is also responsible for DFT design methodology and CAD automation tools development to support the global DFX engineering teams across AMD. THE ROLE We are seeking a highly skilled and experienced DFT Engineering Lead or Manager to lead a Design-for-Test team in developing and implementing advanced DFT IP and design methodologies for complex SoCs / ASICs. The successful candidate will combine deep technical expertise in DFT architecture with strong leadership skills to drive execution, mentor engineers, and collaborate cross-functionally to ensure high-quality, testable designs. THE PERSON : In this role, you will lead a high-performance central DFX design team through full design lifecycle of the state of-the-art industry leading DFT IP, from planning, architecture, design to post-silicon. You will establish a collaborative environment that fosters design innovation and verification best practices. In addition to managing project schedules, deliverables, dependencies, and risk mitigation plans, you will mentor, provide technical guidance, and further develop the team. The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. A global mindset and ability to lead in a multi–site environment are keys to being successful in this role. KEY RESPONSIBILITIES : Team Leadership & Management Lead and mentor a team of DFX engineers, fostering technical excellence, innovation, and collaboration. Manage project priorities, schedules, and deliverables to meet program milestones. Recruit, train, and develop engineering talent. DFT Strategy & Execution Work collaboratively with CDFX function Leads / Managers to define roadmap and drive DFT methodologies, flows, and best practices for complex CPU / GPU / SoC designs. Oversee implementation and verification of DFT RTL build, scan insertion, ATPG, BIST (MBIST, LBIST), boundary scan, and JTAG. Ensure seamless integration of DFT architecture into the overall design flow. Collaborate with SOC design and product engineering teams to ensure testability, debugability and manufacturability. Technical Ownership Provide hands-on guidance in DFT tool and flow usage (Siemens, Synopsys, … etc.) and debug. Drive innovation in low-power test methodologies, hierarchical DFT, and advanced fault models. Cross-Functional Collaboration Partner with architecture, RTL design, verification, and physical design teams to ensure DFX requirements are met. Collaborate with SOC design and product engineering teams on strategic initiatives innovative DFT / DFD design solutions to ensure product testability, debuggability, manufacturability and quality. Interface with foundry and EDA vendors to adopt and deploy cutting-edge DFT solutions. Occasional travel per business need PREFERRED EXPERIENCE : Experienced and skilled DFT design or DV on complex CPU / GPU SOC projects from inception to tape-out Excellent organizational and project management skills Proven experience in leading a medium-sized DFT engineering team (15-20 staff) Strong communications skills. Able to summarize complex problems for executives as well as drill down to details with architects and engineers Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments Must be a self-starter and self-motivated ACADEMIC CREDENTIALS : BSEE, MSEE or equivalent degree Minimum of 15 years of ASIC design or verification experience LOCATION : Bangalore, India #LI-RR1 #LI-Hybrid Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.PMTS SILICON DESIGN ENGINEER ABOUT THE DEPARTMENT Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for high performance, adaptive compute products for data center, embedded, gaming and PC markets. It is also responsible for DFT design methodology and CAD automation tools development to support the global DFX engineering teams across AMD. THE ROLE We are seeking a highly skilled and experienced DFT Engineering Lead or Manager to lead a Design-for-Test team in developing and implementing advanced DFT IP and design methodologies for complex SoCs / ASICs. The successful candidate will combine deep technical expertise in DFT architecture with strong leadership skills to drive execution, mentor engineers, and collaborate cross-functionally to ensure high-quality, testable designs. THE PERSON : In this role, you will lead a high-performance central DFX design team through full design lifecycle of the state of-the-art industry leading DFT IP, from planning, architecture, design to post-silicon. You will establish a collaborative environment that fosters design innovation and verification best practices. In addition to managing project schedules, deliverables, dependencies, and risk mitigation plans, you will mentor, provide technical guidance, and further develop the team. The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills. A global mindset and ability to lead in a multi–site environment are keys to being successful in this role. KEY RESPONSIBILITIES : Team Leadership & Management Lead and mentor a team of DFX engineers, fostering technical excellence, innovation, and collaboration. Manage project priorities, schedules, and deliverables to meet program milestones. Recruit, train, and develop engineering talent. DFT Strategy & Execution Work collaboratively with CDFX function Leads / Managers to define roadmap and drive DFT methodologies, flows, and best practices for complex CPU / GPU / SoC designs. Oversee implementation and verification of DFT RTL build, scan insertion, ATPG, BIST (MBIST, LBIST), boundary scan, and JTAG. Ensure seamless integration of DFT architecture into the overall design flow. Collaborate with SOC design and product engineering teams to ensure testability, debugability and manufacturability. Technical Ownership Provide hands-on guidance in DFT tool and flow usage (Siemens, Synopsys, … etc.) and debug. Drive innovation in low-power test methodologies, hierarchical DFT, and advanced fault models. Cross-Functional Collaboration Partner with architecture, RTL design, verification, and physical design teams to ensure DFX requirements are met. Collaborate with SOC design and product engineering teams on strategic initiatives innovative DFT / DFD design solutions to ensure product testability, debuggability, manufacturability and quality. Interface with foundry and EDA vendors to adopt and deploy cutting-edge DFT solutions. Occasional travel per business need PREFERRED EXPERIENCE : Experienced and skilled DFT design or DV on complex CPU / GPU SOC projects from inception to tape-out Excellent organizational and project management skills Proven experience in leading a medium-sized DFT engineering team (15-20 staff) Strong communications skills. Able to summarize complex problems for executives as well as drill down to details with architects and engineers Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments Must be a self-starter and self-motivated ACADEMIC CREDENTIALS : BSEE, MSEE or equivalent degree Minimum of 15 years of ASIC design or verification experience LOCATION : Bangalore, India #LI-RR1 #LI-Hybrid

Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.