Senior Design Verification Engineer

Senior Design Verification Engineer

We are seeking a seasoned Senior Design Verification Engineer to spearhead our Digital Front-End Test (DFT) strategy and implementation. As a technical leader, you will drive the development of complex SOC / ASIC designs from concept to production.

• You will define and implement DFT architecture, planning, and verification across multiple projects, ensuring world-class testability and manufacturability.
• You will lead the implementation and verification of DFT features, including scan insertion and compression, ATPG pattern generation and fault grading, boundary scan (IEEE 1149.1 / 1149.6), and IJTAG (1687).
• You will manage the end-to-end DFT flow, from RTL to gate-level netlist and silicon bring-up, collaborating with cross-functional teams for seamless integration.

Key Responsibilities

Requirements

Benefits