PPA Optimization Engineer

Position : Physical Design Engineer

Experience : 4+ yrs

Location : Bangalore, Hyderabad

Notice Period : Preferably 0 to 45 days

Summary :

• Strong expertise in Physical Design and RTL-to-GDSII implementation flow, including synthesis, floor planning, place-and-route, timing closure, and sign-off.
• Proven ability to close full-chip and block-level designs from RTL to GDSII, addressing timing, noise, power, IR drop, physical verification, and equivalence checks.
• Hands-on experience with advanced technology nodes (7nm, 5nm, and below), managing challenges related to performance, power, and area (PPA).
• Proficient in Synopsys and Cadence tool suites, including Fusion Compiler, ICC2, Design Compiler, Primetime, StarRC, RedHawk, Innovus, and Calibre.