“Design Verification Engineer – RTL, UVM, Power & Debug Verification”

Exciting Opportunities : Design Verification Engineers 🔹

We are hiring experienced DV engineers for multiple challenging roles in Power, DSP Subsystem, and Debug Subsystem Verification . If you are passionate about RTL verification, SoC / IP-level DV, and cutting-edge semiconductor projects, these opportunities are for you!

JD 1 : End-to-End Power Verification

Experience : 6 years – 2 positions | 4 years – 1 position

Key Skills :

✅ Power-aware verification with UPF annotated RTL

✅ Verification of various power scenarios

✅ Power vector generation – leakage, sleep, clock tree, active use cases

✅ Clock & Reset verification – frequency, glitch, multiple cycle paths

✅ Power switch coverage analysis

✅ Strong DV knowledge – SystemVerilog & UVM

✅ Power-aware GLS with PG netlist

✅ Understanding of power intent, clock, and reset architecture

JD 2 : DSP Subsystem Verification

Experience : 6 years – 2 positions | 4 years – 1 position

Key Skills :

✅ Test case development & performance analysis

✅ DSP or other processor knowledge

✅ Understanding of Neural Networks (NNE)

✅ Performance verification & C-based verification

✅ Strong SystemVerilog & UVM knowledge

JD 3 : Verification of Debug Subsystem

Experience : 6 years – 2 positions | 2 years – 1 position

Key Skills :

✅ End-to-end Debug Subsystem verification

✅ Expertise in RTL DV, GLS, coverage closure

✅ Understanding of ARM Coresight Debug Architecture

✅ Collaborate with architecture & SW teams to define debug system requirements

✅ Define VPlan for CPU debug

✅ ARM-based CPU debug understanding – trace, crash debug

✅ CPU knowledge & C expertise

✅ Strong SystemVerilog & UVM knowledge

Notice Period : Immediate – 30 Days

Location - Bangalore

Contact & Application :

📧 Email : prabhu.p@acldigital.com

📱 WhatsApp : +91 8754387484