Staff Software Development Engineer

Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

Lattice is seeking candidates for the position of Staff Software Development Engineer in FPGA place and route. This is a full-time position located in Pune, India.

Summary :

The successful candidate will join a team designing and developing Lattice FPGA software tools. The candidate will contribute to delivering software solution for Lattice FPGA development with emphasis on Lattice synthesis tool. The candidate is expected to be an expert in FPGA synthesis core engine with knowledge on how to achieve optimal solution for a given architecture and be able to support next generation FPGA with best result in Fmax, Area, Runtime as well as memory utilization The candidate will team up with other synthesis developers and develop synthesis engine for various FPGA products. The responsibility also includes customer support, new software feature support as well as QoR improvement. The candidate is expected to maintain existing software products and interact with other teams to facilitate a value-added solution too.

Accountabilities :

Develop logic synthesis tool for Lattice FPGA products.

Synthesize logic designs from Verilog / VHDL RTL to structural netlist.

Improve synthesis engine QoR.

Create test designs with test benches to verify implementation and ensure high quality.

Qualifications :

BS / MS / PhD in Electrical Engineering or Computer Science or Computer Engineering.

Proficient with C / C++, Verilog / VHDL, logic design, Tcl and shell scripts.

Strong background and experience in data structures and algorithms.

Experience of logic design and EDA software is a must.

Experience of logic optimization and technology mapping development is required.

Experience of FPGA tool development is preferred.

Strong written and verbal communication skills, and collaboration skill.

Experience of multi-processing development is a plus.

Solid understanding in FPGA architectures is a plus.

10+ years of experience in logic synthesis development in FPGA or ASIC domains