Functional Verification Engineer

Job Title : Functional Verification Engineer

Location : Hyderabad

Role Summary

We are looking for an experienced Functional Verification Engineer with strong hands-on expertise in SystemVerilog / UVM. The ideal candidate will be proactive, self-driven, and capable of independently managing deliverables while working on block-level and IP-level verification.

Key Responsibilities

• Develop and maintain block-level testbenches using SystemVerilog / UVM.
• Create and execute verification plans (V-Plans), run regressions, and drive coverage closure.
• Work on testbenches with Real Number Modelling (RNM).
• Perform netlist and gate-level simulations (GLS).

Technical Skills

Strict Checklist (Must-Have Requirements)

Qualifications & Experience