Asic Engineer

Job Summary :

We are seeking a qualified ASIC Digital Frontend Design Automation Engineer to support digital design and verification automation efforts, contributing to the development and maintenance of scalable design flows and methodologies. This role requires strong technical expertise in logic design and verification, scripting, and EDA tool integration. Experience with AI-driven design methodologies is a significant plus.

Key Responsibilities :

Develop and maintain automation scripts for RTL design and verification flows using TCL and Python.

Support and enhance usage of Synopsys VCS, VC-CDC, and VC-Lint or equivalent tools for static and dynamic analysis.

Collaborate with design and verification teams to improve productivity and quality through automation.

Build and maintain regression environments, linting frameworks, and CDC analysis pipelines.

Analyze tool outputs and provide actionable insights to design teams.

Document automation flows and provide training / support as needed.

Explore and integrate AI-based design and verification flows to improve efficiency and scalability.

Qualifications :

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related discipline.

5–6 years of experience in ASIC frontend design and automation.

Solid understanding of logic design and logic verification methodologies.

Hands-on experience with Synopsys VCS, VC-CDC, and VC-Lint or similar tools.

Proficiency in TCL and Python scripting.

Familiarity with version control systems (e.G., Git) and CI / CD practices.

Strong analytical and communication skills.

Preferred Qualifications :

Experience with formal verification tools and methodologies.

Exposure to other EDA tools (e.G., Cadence, Mentor).

Knowledge of SystemVerilog and UVM is a plus.

Experience with AI / ML-based design automation tools or frameworks.