Job Description :
We are seeking a highly motivated and experienced Principal / Staff SerDes Design Engineer to join our team developing next-generation high-performance wireline transceivers. You will design high-speed and high-performance AMS circuits for SerDes PHY IPs implemented in advanced technology nodes.
This role requires strong technical depth in SerDes architectures, analog / mixed-signal circuit design, and hands-on experience in validating high-speed PHY designs.
Key Responsibilities
- Design and develop high-speed SerDes circuits , including TX, RX, PLL, CDR, DLL, VCO, phase interpolators, bias generators, and clocking circuits.
- Evaluate and implement different analog and AMS topologies to achieve best-in-class Power, Performance, and Area (PPA) .
- Perform detailed transistor-level circuit simulations, modeling, and analysis using industry-standard tools.
- Work closely with layout engineers to ensure optimum layout practices and physical implementation.
- Drive silicon validation, bring-up, and lab characterization of SerDes blocks.
- Debug complex AMS issues and provide timely technical resolutions.
- Collaborate with cross-functional teams to define specifications and ensure system-level alignment.
- Mentor junior engineers and contribute to team capability building and knowledge sharing.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering or related field.10+ years of hands-on experience in SerDes circuit design.Strong background in analog / mixed-signal design , high-speed links, and clocking circuits.Expertise in high-speed digital design , equalization, and signal integrity concepts.Proficiency with simulation tools such as Cadence Virtuoso, Spectre, HSPICE , etc.Hands-on experience with lab equipment (oscilloscope, BERT, VNA, spectrum analyzer, etc.).Excellent debugging, problem-solving, and communication skills.