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Design Verification Engineer

Design Verification Engineer

ACL Digitaljunagadh, India
1 day ago
Job description

#ACL Digital is Hiring : GPM Subsystem Verification Engineer

Must-have : UVM, System Verilog, IP Verification

Preferred : Power Management IP, Firmware DV, Python / Perl

Full-cycle DV : test plan → tape out

Collaborate with top DV, design & architecture teams

Apply / Refer :

#ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog

#PowerManagementIP #HyderabadJobs #VLSICareers

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Design Verification Engineer • junagadh, India

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