Sr rtl principal design engineer

RTL Design Engineer for Interface Controller IP development team.

Position is based in Bangalore or Noida.

The role would include design and support of the RTL of the PCIe / CXL / IDE / UALink IP solution of Cadence.

The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

Position Requirements :

BE / BTech / ME / MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.

8-16 years of core RTL Design experience using Verilog is a must.

System Verilog experience and experience with UVM based environment usage / debugging is required.

PCIe / CXL / IDE experience is needed. Prior experience in implementation of complex protocols is a must.

Prior experience in IP development teams would be an added advantage.

Scripting knowledge is an advantage