Senior Design Verification Engineer

Location : Hybrid

Job Type : Full-Time

Posted Date : 6 / 30 / 2025

About The Role

Job Overview : We are looking for an experienced Senior Design Verification Engineer with a strong background in System Verilog and UVM , capable of independently owning and driving the verification of blocks, subsystems, or full SoCs. The ideal candidate will have expertise in industry-standard protocols and power-aware verification, with hands-on experience in building and executing scalable verification environments.

Must-Have Skills :

• Strong hands-on experience with System Verilog (SV) and UVM.
• Proficient in Testbench Architecture & Development
• Expertise in verifying at least one of the following protocols : o PCI Express, UCIe, CXL, or NVM o AXI, ACE, or CHI o Ethernet, RoCE, or RDMA o DDR, LPDDR, or HBM Key Responsibilities :
• Own and lead the verification of digital blocks, subsystems, or SoCs
• Develop scalable and reusable UVM-based verification environments
• Execute test plans, write test cases, and drive coverage closure
• Collaborate with architecture, design, and firmware teams
• Debug and root-cause issues across the design-verification stack
• Contribute to regression automation and continuous integration workflows

Required Experience :

verification

If you are interested in this role, please mail your resume to [HIDDEN TEXT] or [HIDDEN TEXT]

Skills Required

Ace, PCI Express, Uvm, Axi, Ddr, Ethernet, System Verilog