UPF & Power Simulation

Role : UPF & Power Simulation

Preferred experience : 8+ Years

Location : Hyderabad

Availability : Immediate – 30 days

Job Description :

The responsibilities will majorly include :

• Understanding of power domains and HW programming guide sequences
• Develop test plan to verify all low power states
• Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals
• Exploring innovative dynamic or static methodologies by engaging with EDA vendors
• Strong System Verilog / UVM based verification skills Experience with Assertion coverage-based verification methodology
• Experience in formal / static verification methodologies will be a plus
• Good understanding of low power design techniques
• Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.
• Experience with UPF / CPF based power aware verification.
• Experience with Synopsys NLP (native Low Power) tool.
• Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus
• Proficiency in Low-Power standards like UPF / CPF.
• Working knowledge on UPF based RTL / PGPIN simulations.
• Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs).
• Excellent analytical and problem-solving skills with a focus on power optimization.

Skills Required

SOC design, ASIC Design, System Verilog