Physical Design Lead

minimum Qualifications :

Good hands-on experience on Floorplanning, PNR and STA flows

Good knowledge on Placement / Clock Tree Synthesis (CTS), optimization, etc

Good understanding on signoff domains– LEC / CLP / PDN knowledge, etc

Good knowledge on Unix / Linux – Perl / TCL fundamentals / scripting

Principal Duties and responsibilities :

Complete ownership on PNR implementatio n (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.

Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)

Quick learner with good analytical and problem solving skills

Qualifications :

• 20+ years Hardware Engineering experience or related work experience.
• 17+ years experience with PNR flow in latest tech nodes (e.G., 4nm / 5nm / 7nm / 10nm