Design Engineering Manager

Requirements / Qualifications :

• Bachelor’s or Master’s degree in Electrical / Electronics Engineering or related discipline.
• 12–15 years of relevant industry experience, including 2–3 years in technical or people leadership roles.
• Strong hands-on experience in RTL design (Verilog / VHDL / SystemVerilog) and SoC / Subsystem development .
• Solid understanding of ARM CPU-based architectures , AMBA interconnects (AXI, AHB, APB), and PCIe protocols.
• Proficiency in Synthesis, STA, and timing closure flows .
• Experience with linting, CDC, DFT , and low-power design techniques .
• Familiarity with C / C++ modeling and design validation environments preferred.
• Working knowledge of AI / ML-based design optimization or automation scripting (Python / TCL / Perl) is a plus.
• Excellent analytical, communication, and cross-functional collaboration skills.
• Highly self-driven, detail-oriented, and committed to design quality and schedule delivery.