Layout / Mask Designer 3_INR
Location : Hyderabad
TSMC : Yes
Description :
Responsible for Design and development of critical analog, mixed-signal, custom digital
block, and full chip level integration support.
- Expertise in Cadence VLE / VXL and Mentor Graphic Caliber DRC / LVS is a must.
- Perform layout verification like LVS / DRC / Antenna, quality check and support
documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.Excellent problem-solving skills in physical verification of custom layout.Demonstrate high quality and accurate execution to meet project schedule / milestones inmultiple project environment.
Ability to guide junior team-members in their execution of Sub block-level layouts & reviewcritical items.
Contribute to effective project-management.Effectively communicating with Local engineering teams to assure the success of layoutproject.
Educational Background
BE or MTech in Electronic / VLSI Engineering5 + year experience in analog / custom layout design in advanced CMOS process.NOTE :
custom layout or analog layout with TSMC 3nm / 5nm7nm & 5+ exp