Asic Rtl Design Engineer

ASIC RTL Design Engineer

Location : Bangalore

Job Description : Skills & Experience :

• 3-5 years of experience in ASIC front end design and quality check.
• Strong fundamental knowledge of digital design, Verilog, and scripting language.
• Experience in multiple clock and voltage domain design.
• Working knowledge for FE flows like Lint, CDC, synthesis, and other quality checks.
• Understanding of UPF and experience in low power checks is preferred.
• Understanding of memory controller and / or cache controller and / or memory subsystem is add-on.
• Must possess good communication skills;

prior experience working with global teams is desirable.

Responsibilities :