Senior Lead Engineer - PD

Job Requirements

Roles & Responsibilities

• Ownership of end-to-end Physical Design flow from RTL to GDSII for complex SoC / ASIC designs.
• Responsible for floorplanning, partitioning, placement, CTS, routing, and physical verification (DRC / LVS / Antennas etc.).
• Timing closure activities across PVT corners, multi-mode multi-corner (MMMC) analysis.
• Work on power planning and optimization (IR drop, EM analysis, low-power design methodologies).
• Handle STA (Static Timing Analysis) using tools like PrimeTime / Tempus and drive closure.
• Collaborate closely with RTL designers, DFT, STA, and verification teams to resolve issues proactively.
• Experience in synthesis and formal equivalence checking (LEC) to ensure design quality.
• Familiarity with signoff methodologies and tapeout process.
• Mentor and guide junior engineers within the team, review their work, and drive best practices.
• Contribute to methodology improvements, flow automation, and scripting.

Key Skills

Cadence (Innovus, Voltus, Tempus, LEC ) or Synopsys (PrimeTime, StarRC)

Desired Profile

Work Experience

Cadence (Innovus, Voltus, Tempus, LEC ) or Synopsys (PrimeTime, StarRC)

Skills Required

Sta, Shell, Scripting, lec, synopsys primetime , Physical Verification, Perl, cpf , Tcl