SystemVerilog / UVM Verification Engineer
ProxeleraHyderabad, Republic Of India, IN1 day ago
Job descriptionStrong hands-on coding experience in SystemVerilog / UVM . Proven experience in block / IP-level verification ; Pure DV role with expertise in developing TB environments and components GLS experience : 0-delay and timing simulations Experience in integrating Real Number Models into the TB and running digital simulations Strong experience in IP verification coverage closure (100% code + 100% functional coverage) Typically expected in engineers with 6+ years of DV experience Education : Bachelor’s degree or higher in Electronics or related field. Experience : 5–10 years in Functional Verification.
Job Title : Functional Verification Engineer
Location : Hyderabad
Role Summary
We are looking for an experienced Functional Verification Engineer with strong hands-on expertise in SystemVerilog / UVM . The ideal candidate will be proactive, self-driven, and capable of independently managing deliverables while working on block-level and IP-level verification.
Key Responsibilities
- Develop and maintain block-level testbenches using SystemVerilog / UVM.
- Create and execute verification plans (V-Plans) , run regressions, and drive coverage closure .
- Work on testbenches with Real Number Modelling (RNM) .
- Perform netlist and gate-level simulations (GLS) .
Technical Skills
subsystem / SoC-level experience is an added advantage.
Strict Checklist (Must-Have Requirements)
Qualifications & Experience
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Verification Engineer • Hyderabad, Republic Of India, IN