General Summary
Qualcomm Chennai seeks an STA (Static Timing Analysis) and Synthesis Engineer to work collaboratively with cross-functional teams. This role involves various stages of SoC / core design and development, focusing on synthesis and timing closure.
Key Responsibilities
- Perform synthesis, static timing analysis (STA), and logical equivalence checking (LEC) of SoCs and cores.
- Achieve full-chip and block-level timing closure.
- Handle IO budgeting for blocks.
- Conduct logical equivalence checks between RTL and netlist, as well as netlist-to-netlist.
- Apply low-power design techniques such as clock gating, power gating, and multi-voltage (MV) designs.
- Implement ECO (Engineering Change Order) timing flows.
- Write and maintain automation scripts, proficient in TCL and Perl scripting languages.
Minimum Qualifications
Education and Experience :Bachelor's degree in Computer Science, Electrical / Electronics Engineering, or related field with 3+ years of hardware engineering or related experience.ORMaster's degree with 2+ years experience.ORPhD with 1+ year experience.At least 4 years of relevant experience preferred.Ideal Skills and Competencies
Strong knowledge in synthesis and STA tools.Experience with logical equivalence checking.Familiarity with low-power design methodologies.Proficiency in scripting (TCL, Perl).Ability to collaborate effectively with cross-functional engineering teams.Skills Required
Sta, Synthesis, Perl, Scripting Languages, Physical Design, hardware engineering , Tcl