Physical Design Engineer

Physical Design Engineers

Experience : 3-5 years

Location : Bangalore

JOB DESCRIPTION

Candidate should have hands on experience in PnR, timing closure, PDN and physical verification. He will be responsible for driving SerDes block level implementation from Netlist to GDSII, ensuring PPA goals are met.

Strong expertise in PnR tools [Preferrably Cadence Innovus ]

Solid understanding of timing analysis using tools like PrimeTime or Tempus

Experience with PDN design, IR drop analysis and EM verification.

Familiarity with Physical verification tools [Eg : Calibre ]

Knowledge of scripting lanaguages for any minor automation requirement [TCL, Python ..]

Experience with advanced nodes [Eg 5nm, 3nm...etc]

Since the MSIP involves complex custom requirements related to clocking and placement and higher frequency design closures —rather than being driven by gate count—we expect the candidate to take full ownership of the implementation and all associated signoff activities.

Interested,please drop your updated resume to janagaradha.n@acldigital.com