Analog Layout Engineer

Job Summary

Title / Position : Analog Layout Engineer

Experience : 2-12 years

Location : Bangalore , Hubli

About us :

Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions.

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 3500+ employees worldwide,

Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose.

Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one’s intellect, skills and growth.

Responsibilities :

Layout Design Engineer

Worked as layout design engineer for complete cycle of the project.

To prepare the layouts from scratch and deliver the cells on time with all the guidelines and verification checks.

Qualification : BE / BSC / Diploma

Technical Skillset required :

Exp of   Layout Design Knowledge in CMOS lower process nodes ranging from 180nm to 3nm.

Must have experience which includes one or more of Analog / SERDES IPs such as ADC / DAC / PLL / DLL / Thermal Sensor / HBM / DDR / LDO / GPIO / USB / LVDS / MIPI / PCIe

The candidate should have strong layout design concepts starting from bump plan, floor planning, power grid design, FIN FET layouts, Analog layout matching, LVS and DRC clean up, EMIR clean up.

Hands on Experience in Floor Planning, Placement and routing of blocks and integration of IO’s

Expertise in handling ESD, LUP, Antenna, and a nalyzing / fixing EMIR issues.

Exp ertise in Physical Verification checks (DRC, LVS, DFM, Antenna, L atchup Checks & PERC)

Experience with Std EDA tools, Cadence tool, and physical verification tools

The candidate needs to have s trong communication skills to allow teamwork and problem    solving.

Good understanding of Layout Dependent Effects and implementation in layout

Capable of working independently and with team and coordinating with designers

Scripting skills with Perl and Cadence SKILL is a plus.

Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one’s intellect, skills, creates and environment for people who thrive for success and grow with the organization's growth. Tessolve has something unique to offer to everyone depending on their interest levels.

Disclaimer :

At Tessolve , we are committed to fostering a workplace that embraces and celebrates diversity in all its forms. We believe that diverse teams drive innovation, creativity, and success. We are dedicated to creating an inclusive environment where all employees, regardless of their race, color , religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status, feel valued and respected. We believe in fair and equitable treatment for all employees and aim to eliminate any biases or barriers that may hinder personal or professional growth.