Job Description – Physical Design Engineer / Sr. Physical Design Engineer
Position : Physical Design Engineer / Sr. PD Engineer
Location : Bengaluru / Hyderabad
Experience : 3–10 Year
Company : LeadSoc Technologies Pvt Ltd
Role Overview :
We are looking for a highly skilled Physical Design Engineer to work on complex SoC and block-level implementation from Netlist-to-GDSII . The ideal candidate should have strong hands-on experience in PnR tools , timing closure , low-power methodologies , and sign-off flows , along with strong problem-solving and communication skills.
Key Responsibilities :
- Work on Block / SOC level Physical Design from RTL to GDSII.
- Execute complete PD implementation flow including floorplanning, power planning, placement, CTS, routing, extraction, and timing closure.
- Handle low-power design methodologies including UPF / CPF, power domains, isolation, retention cells, etc.
- Perform congestion analysis, timing analysis , and deliver improved QoR across design stages.
- Run physical verification and sign-off checks :
- STA
- DRC / LVS / Antenna
- ERC
- IR / EM analysis
- LEC
- Power analysis
- Perform ECO implementation (timing and functional).
- Collaborate with RTL, DFT, architecture, and sign-off teams to ensure design convergence.
- Drive block-level and top-level closure with strong ownership and leadership.
- Utilize scripting (Perl / TCL) for flow automation and efficiency improvements.
- Ensure all deliverables meet schedule, quality, and performance targets.
Required Skills & Experience :
Strong experience in Netlist-to-GDSII / Physical Design / PnR / APR flows .Hands-on knowledge of :Synopsys ICC2 , Fusion Compiler,Cadence Innovus , Tempus, VoltusIn-depth understanding of PD stages : Floorplan, Placement, CTS, Routing, Extraction, Sign-off .Solid understanding of timing, congestion, SI, IR / EM , and closure methodologies.Experience in ECO (timing and functional) implementation.Strong Perl / TCL scripting skills for automation.Good leadership, communication, and problem-solving skills.Self-driven, proactive, and results-oriented (“Go-getter attitude”).Good to Have :
Experience in advanced nodes (e.g., 7nm / 5nm / 3nm).Knowledge of multi-domain power intent (UPF).Exposure to cloud-based or distributed PD flows.Education :
Bachelor’s or Master’s degree in Electronics / Electrical / VLSI / Computer Engineering or related field.